1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a metallization process for forming a refractory metal silicide in a large scale integrated circuit, which is capable of particularly preventing a retardation in a silicide formation reaction on an N-type diffused region.
2. Description of Related Art
With an elevated integration density of CMOS (complementary MOS (metal oxide semiconductor field effect transistor)) type semiconductor devices, a junction depth becomes shallow, and therefore, a resistance of an impurity diffused layer increases. This is a hindrance in manufacturing a semiconductor device having a high operation speed. In this situation, there has been used a silicide technology for forming a refractory metal silicide, in a self-alignment manner, on a diffused layer or a polysilicon gate electrode.
Referring to FIGS. 1A to 1E, there are shown diagrammatic partial section views of a semiconductor device for illustrating a process of forming a refractory metal silicide on the basis of a prior art silicide technology.
As shown in FIG. 1A, on P-type silicon substrate 1 having an N-well 2 selectively formed therein and a field oxide film 3 formed thereon to confine a device formation region on the N-well and on the P-type substrate 1, respectively, a gate electrode structure composed of a gate oxide film 4 and a polysilicon gate electrode 5 is formed in accordance with a conventional CMOS semiconductor device manufacturing process. Then, as shown in FIG. 1B, a first mask (not shown) is deposited to cover the N-well 2, and an N-type impurity, for example, arsenic, is implanted into the substrate 1 by using the polysilicon 5 as a mask, to form a pair of N-type diffused (source/drain) regions 8 in the substrate 1.
Thereafter, as shown in FIG. 1C, the first mask is removed, and a second mask (not shown) is deposited to cover the substrate 1 including the N-type diffused regions 8. A P-type impurity, for example, boron fluoride, is implanted into the N-well 2 by using the polysilicon 5 as a mask, to form a pair of P-type diffused (source/drain) regions 9 in the N-well 2. Then, the second mask is removed.
As shown in FIG. 1D, a film 10 of a refractory metal such as titanium is deposited on the whole surface of the substrate by sputtering, and a first heat treatment is carried out in a nitrogen atmosphere, so that a silicide formation reaction is caused to occur simultaneously on the N-type diffused regions 8 and on the P-type diffused regions 9.
Thereafter, unreacted metal titanium is removed by etching, and a second heat treatment is carried out to form a titanium silicide film 11 on the N-type diffused regions 8, on the P-type diffused regions 9 and the polysilicon gate electrodes 5, as shown in FIG. 1E.
In the above mentioned process, when the silicide formation reaction is caused to occur in the first heat treatment, since the silicide formation reaction is influenced by impurities implanted in the N-type diffused layers, the film thickness of the titanium silicide formed on the P-type diffused layer is difference from the film thickness of the titanium silicide formed on the N-type diffused layer. Therefore, it is difficult to set an optimum heat treatment condition common to both the N-type diffused layer and the P-type diffused layer. In other words, since the silicide formation reaction is retarded on the N-type diffused layer, the silicide having only a thin film thickness is formed on the N-type diffused layer, so that the silicide film sheet resistance inevitably increases on the N-type diffused layer. On the other hand, since the silicide formation reaction is hardly retarded on the P-type diffused layer, so that the silicide having a thick film thickness is formed on the P-type diffused layer, so that an on-current drops on the P-type diffused layer, and a leakage occurs between a gate and a source/drain region.
Referring to FIG. 2, there is shown a diagrammatic partial sectional view of a semiconductor device for illustrating another prior art process of manufacturing a semiconductor device, which is disclosed by Japanese Patent Application Laid-open No. JP-A-62-013076.
As shown in FIG. 2, on a silicon substrate having a field oxide film 3 for device isolation, a gate oxide film 4 is formed, and a polysilicon gate is formed on the gate oxide film 4. In order to prevent the silicide formation reaction from being retarded by impurities, the polysilicon gate has a double layer structure composed of a first polysilicon layer 5A having a high concentration of impurity formed on the gate oxide film 4 and a second polysilicon layer 5B having a low concentration of impurity formed on the first polysilicon layer 5A. A refractory metal deposited on the polysilicon gate thus formed reacts on only the polysilicon layer 5B having a low concentration of impurity, so that a refractory metal silicide formation reaction is not retarded.
However, the prior art process proposed by JP-A-62-013076 relates to only the silicide formation reaction on only the polysilicon gate electrode, and therefore, cannot avoid the retardation of the silicide formation reaction on the N-type diffused regions (8 shown in FIG. 1E). Furthermore, JP-A-62-013076 describes that the impurity concentration in the polysilicon layer 5B having a low concentration of impurity is a half of the impurity concentration in the polysilicon layer 5A having a high concentration of impurity. However, it is not sure that, in the disclosed semiconductor device manufacturing method, this concentration distribution has an effect of preventing the silicide formation reaction retardation, but rather, it is considered to be impossible to sufficiently prevent the silicide formation reaction retardation.